m21262 Mindspeed Technologies, m21262 Datasheet - Page 64
m21262
Manufacturer Part Number
m21262
Description
Cdr/reclocker With 4 1 Input Multiplexer
Manufacturer
Mindspeed Technologies
Datasheet
1.M21262.pdf
(71 pages)
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3.1.26
Table 3-27.
21262-DSH-001-C
Bits
7:6
5:4
1:0
3
2
Type
R/W
R/W
R/W
R/W
R/W
Output Buffer Control for CDR/RCLK (Out_ctrl: Address 43h)
Output Buffer Control for CDR/RCLK
Default
10b
00b
00b
0b
1b
outlvl
Reserved
data_pol_flip
dataout_en
MSPD internal
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Label
Determines the output swing of a data buffer for CDR/RCLK.
In PCML mode:
00b: Power down
01b: 500 mV
10b: 900 mV
11b: 1200 mV
For LVDS, the output swing is reduced to:
00b: Power down
01b: RRL 390 mV
10b: GPL 700 mV
11b: 940 mV
For LVPECL, the output swing is increased to:
00b: Power down
01b: 900 mV
10b: Standard (low specification side) 1200 mV
11b: Standard (nominal) 1600 mV
For InfiniBand, the output swing is increased to:
00b: Power down
01b: 900 mV
10b: 1200 mV
11b: Standard (nominal) 1400 mV
N/A
Flips the polarity of the output data.
0b: Normal
1b: Polarity flip
Enables the data output driver.
0b: Data output disabled and powered down
1b: Data output enabled to level specified in Out_ctrl [7:6]
N/A
®
Description
Registers
56
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