m21262 Mindspeed Technologies, m21262 Datasheet - Page 62

no-image

m21262

Manufacturer Part Number
m21262
Description
Cdr/reclocker With 4 1 Input Multiplexer
Manufacturer
Mindspeed Technologies
Datasheet
3.1.22
Table 3-23.
3.1.23
Table 3-24.
21262-DSH-001-C
Bits
Bits
7:1
0
7
6
5
4
3
2
1
0
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N/A
R
CDR/RCLK Loss of Activity Register Alarm Status (Alarm_LOA: Address 31h)
CDR/RCLK Control Register A (RCLK_ctrlA: Address 40h)
CDR/RCLK Loss of Activity Register Alarm Status
CDR/RCLK Control Register A
0000000b
Default
Default
N/A
0b
0b
0b
0b
1b
1b
1b
1b
MSPD internal
LOL
softreset
MSPD internal
inh_force
MSPD internal
autoinh_en
MSPD internal
MSPD internal
MSPD internal
Mindspeed Proprietary and Confidential
Mindspeed Technologies
Label
Label
N/A
0b = LOA alarm de-asserted
1b = LOA alarm asserted
NOTE: After a clear (Globctrl [0] = 1), this register is cleared and will
latch any new alarms that make a L to H transition, and set any pre-
existing alarm conditions to H.
Resets individual CDR/RCLK (setup registers remain unchanged; need
to softreset after rate change).
0b: Normal operation
1b: Reset single CDR/RCLK only
N/A
Manual control of the output inhibit if RCLK_ctrlA [3] = 0.
0b: Normal operation
1b: Forced inhibit
N/A
Auto inhibit of the output (DoutP = H, DoutN = L) if CDR/RCLK has a
LOL condition.
0b: Auto inhibit disabled, RCLK_ctrlA [5] determines inhibit force state
1b: Auto inhibit enabled
N/A
N/A
N/A
®
Description
Description
Registers
54

Related parts for m21262