m21262 Mindspeed Technologies, m21262 Datasheet - Page 49

• Manufacturer Part Number: m21262
• Description: Cdr/reclocker With 4 1 Input Multiplexer
• Manufacturer: Mindspeed Technologies

2.7
A single power plane for the AVdd_IO and AVdd_Core power supplies with bulk capacitors (typically 10
distributed throughout the board will mitigate most power-rail related voltage transients. A bulk capacitor should
also be placed where the power enters the board. It is recommended that decoupling capacitors only be routed
directly to the power pin if they can be placed within 1/8 of an inch of the pin. Decoupling capacitors should be
dispersed around the outside of the device on the top side and underneath the IC on the bottom side of the board.
It is recommended that 0.1
required on each pin, but should be dispersed uniformly to filter different frequencies of noise.
A continuous ground plane is the best way to minimize ground impedance. Return currents and power supply
transients produce most ground noise during switching. Reducing ground plane impedance minimizes this effect.
There is a high frequency decoupling effect from the capacitive effect of power/ground planes and this can be used
to help minimize the amount of high frequency decoupling capacitors.
High-speed PCML signals should be routed with 50
differential pair. Buried strip line is recommended for internal layers while microstrip line is used for signals routed
on surface layers. There should be no discontinuity in the ground planes during the path of the signal traces.
Impedance discontinuities occur when a signal passes through vias and travels between layers. It is recommended
to minimize the number of vias and layers that the transmit/receive signals travel through in the design. The system
PCB should be designed so that high-speed signals pass through a minimal number of vias and remain on a single
internal high-speed routing layer.
When vias need to be used, the via design should match the transmission line impedance by observing the
following:
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In general, some general rules for PCB design for high data rates are:
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For high-speed differential signals, the trace lengths of each side of the differential pair should be matched to each
other as much as possible. The skew between the P and N signals in a differential pair should be tightly controlled
in order for the differential receiver to detect a valid data transition. When matching trace lengths within a
differential pair, care should be taken to avoid introducing large impedance discontinuities. The figures below show
two methods of matching the trace lengths for a differential pair.
Typically, the preferred solution for trace length matching in differential pairs is to use a serpentine pattern for the
shorter signal as shown in
impedance discontinuity while making both trace lengths equal.
21262-DSH-001-C
Avoid through-hole vias; they cause stubs by extending the full cross-section of the PCB despite the fact that
the layer change requires only a small length via (as in the case of adjacent layers). Use short blind vias.
Avoid layer changes in general as the characteristic impedance of the transmission line changes as a result.
PCB trace width for high-speed signals should closely match the SMT component width, so as to prevent stub
effects from a sudden change in stripline width. A gradual increase in trace width is recommended as it meets
the SMT pad.
The PCB ground/power planes should be removed from under the I/O pins so as to reduce parasitic
capacitance.
High-speed traces should avoid sharp changes in direction. Using large radii will minimize impedance
changes. Avoid bending traces by more than 45 degrees; otherwise, provide a circular bend so as to prevent
the trace width from widening at the bend.
Avoid trace stubs by minimizing components (resistors, capacitors) on the board. For instance, a termination
resistor at the input of a receiver will inflict a stub effect at high frequency. Termination resistors integrated on
chip will eliminate the stub. Components designed to DC couple to one another avoid the need for coupling
capacitors and the inherent stubs created from them.
PCB High-Speed Design and Layout Guidelines
Figure
µ
F and 0.01
2-14. Using a serpentine pattern for length matching will minimize the differential
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µ
F decoupling capacitors be used. All three capacitor values are not
Ω
equal length traces for P and N signals within each
®
Product Specifications
µ
F)
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