m21262 Mindspeed Technologies, m21262 Datasheet - Page 20

• Manufacturer Part Number: m21262
• Description: Cdr/reclocker With 4 1 Input Multiplexer
• Manufacturer: Mindspeed Technologies

Functional Description
peaking will be less than 0.1 dB. When DRD is not equal to 1, the bandwidth at DRD = 1 scales by the DRD divide
ratio. For example, if the LBW is 2.38 MHz at 2 x HD-SDI with DRD = 1, then if DRD = 2 for HD operation, the LBW
will be 1.19 MHz. In general, the default bandwidth will meet SMPTE specifications for all bit rates down to 143
MHz. Internal filter components assure that the peaking will not exceed 0.1 dB for all DRDs up to 16. In the
hardwired mode, the LBW will be properly set for the hardwired bit rates. In the serial register mode, the default
bandwidth scales automatically with the input bit rate, and the bandwidth can be tuned through registers.
The CDR/RCLK requires an external reference clock to be connected to the RefClkP/N pins. The CDR/RCLK
contains an internal frequency prescaler that allows a single reference to be used for multiple bit rates and thereby
ease the burden of having to route and switch multiple frequency references.
Frequency acquisition is accomplished with two key sections. The first section is a secondary phase/frequency lock
loop (P/FLL) that drives the VCO towards the desired frequency. The second section is the loss-of-lock circuitry
(LOLCir), that turns on or off the secondary P/FLL. In general LOL has register bits (Alarm_LOL) which are active
high, and pins (xLOL[3:0]) which are active low, for wired OR use to be wired OR externally. In the general context,
they will be referred to as LOL which is active H. With both methods, frequency acquisition takes place when the
LOLCir determines an out of lock condition (LOL = H) for each CDR/RCLK, when the VCO frequency exceeds a
given range (window). LOLCir enables the secondary P/FLL to drive the VCO close to the desired frequency (the
input data bit rate). When the VCO falls within a given frequency range where the CDR/RCLK loop can acquire
phase lock, LOLCir turns off the secondary P/FLL and sets LOL = L, allowing the CDR/RCLK to achieve phase
lock. During this time, LOLCir continues to monitor the frequency difference and will signal a LOL = H to start the
acquisition routine again; if the frequency falls out of range. The LOLCir range is fixed in hardwired mode, and
programmable in 2-wire or 4-wire serial interface mode. In general, the frequency threshold (window) for
LOL = H-to-L and LOL = L-to-H are different to prevent LOL from toggling when the frequency is near one of the
windows. These registers also control the frequency acquisition time. Suggested values are given in this document
for general robust operation, and are used as register defaults, however, the programmability of the registers allow
for optimization based on a given application (e.g. faster lock times).
1.1.15
General CDR/RCLK Features
The CDR/RCLK is reset upon xRST = L, Mastreset = AAh, or upon power up. A soft reset through
RCLK_ctrlA [3] = 1b resets the CDR/RCLK state machine, and presets the CDR/RCLK to an out-of-lock condition,
however, the register contents that are related to CDR/RCLK setup are unchanged. It is required to force a soft
reset if the bit rate is dynamically changed. The soft reset register bit needs to be cleared for proper operation. In
general, a reset during operation will cause bit errors, until the CDR/RCLK achieves phase lock.
By default, the CDR/RCLK is active and powered up for normal operation. By setting RCLK_ctrlB [7:6] = 11b, the
CDR/RCLK can be bypassed and powered down, to allow for nonstandard bit rates, or to save power when the
CDR/RCLK is not required at lower bit rates. When RCLK_ctrlB [7:6] = 01b, the CDR/RCLK is bypassed so the
output data is not retimed but active (VCO locked to the input data). In the last mode with RCLK_ctrlB [7:6] = 10b,
the CDR/RCLK is powered down, and all signals along the input and output paths are also powered down, to save
power. In this case, the input data does not reach the output.
To prevent the propagation of noise in the case where there is a LOL condition, the CDR/RCLK contains an auto-
inhibit feature, which is enabled by default. When LOL is active, the output of the CDR/RCLK is fixed at a logic high
state (DoutP = H, DoutN = L). This feature can be disabled by setting RCLK_ctrlA [3] = 0b, which allows
RCLK_ctrlA [5] to either force an inhibit (1b) or to never inhibit (0b).
In some applications, the optimal data sampling point is not in the middle of the data eye. By default, the CDR/
RCLK achieves phase lock very near the center of the eye. For optimal performance (jitter tolerance), the actual
sampling point can be adjusted with Phadj_ctrl [3:0]. The adjustment range is from -122.5 mUI to +122.5 mUI with
17.5 mUI steps.
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Mindspeed Technologies
21262-DSH-001-C
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