m21262 Mindspeed Technologies, m21262 Datasheet - Page 8

• Manufacturer Part Number: m21262
• Description: Cdr/reclocker With 4 1 Input Multiplexer
• Manufacturer: Mindspeed Technologies

Table 2-11. CDR/RCLK High-Speed Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Table 2-12. CDR/RCLK Alarm Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 2-13. SMPTE Jitter Tolerance Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Table 2-14. Loop Bandwidths for Typical Video Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 3-10. Built In Self-Test (BIST) Transmitter Channel Select (BISTtx_chsel: Address 14h) . . . . . . . . . . . . . . . . . . . . . . . .48
Table 3-11. Built In Self-Test (BIST) Transmitter Main Control Register (BISTtx_ctrl: Address 15h) . . . . . . . . . . . . . . . . . . . .48
Table 3-12. Built In Self-Test (BIST) Transmitter PLL Loss of Lock Register
Table 3-13. Built In Self-Test (BIST) Transmitter PLL Control Register A (BISTtx_PLL_ctrlA: Address 18h) . . . . . . . . . . . . . .50
Table 3-14. Built In Self-Test (BIST) Transmitter PLL Control Register B (BISTtx_PLL_ctrlB: Address 19h) . . . . . . . . . . . . . .51
Table 3-15. Built In Self-Test (BIST) Transmitter PLL Control Register C (BISTtx_PLL_ctrlC: Address 1Ah) . . . . . . . . . . . . . .51
Table 3-16. Built In Self-Test (BIST) Transmitter 20 bit User Programmable Pattern (BIST_pattern0: Address 1Bh) . . . . . . .51
Table 3-17. Built In Self-Test (BIST) Transmitter 16/20 bit User Programmable Pattern (BIST_pattern1: Address 1Ch) . . . . .52
Table 3-18. Built In Self-Test (BIST) Transmitter 16/20 bit User Programmable Pattern (BIST_pattern2: Address 1Dh) . . . . .52
Table 3-19. Built In Self-Test (BIST) Transmitter Alarm (BISTtx_alarm: Address 1Fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 3-20. Internal Junction Temperature Monitor (Temp_mon: Address 20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 3-21. Internal Junction Temperature Value (Temp_value: Address 21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 3-22. CDR/RCLK Loss of Lock Register Alarm Status (Alarm_LOL: Address 30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 3-23. CDR/RCLK Loss of Activity Register Alarm Status (Alarm_LOA: Address 31h) . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 3-24. CDR/RCLK Control Register A (RCLK_ctrlA: Address 40h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Table 3-25. CDR/RCLK Control Register B (RCLK_ctrlB: Address 41h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 3-26. CDR/RCLK N Control Register C (RCLK_ctrlC: Address 42h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 3-27. Output Buffer Control for CDR/RCLK (Out_ctrl: Address 43h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 3-28. Output Buffer Pre-Emphasis Control for Output (Preemp_ctrl: Address 44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 3-29. Input Equalization Control for Output (Ineq_ctrl: Address 45h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 3-30. CDR/RCLK Loop Bandwidth and Data Sampling Point Adjust (Phadj_ctrl: Address 46h) . . . . . . . . . . . . . . . . . . .58
Table 3-31. CDR/RCLK LOL Window Control (LOL_ctrl: Address 49h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Table 3-32. Jitter Reduction Control (Jitter_reduc: Address 4Ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
21262-DSH-001-C
Register Table Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Global Control (Globctrl: Address 00h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Input Multiplexer Setting (mux_ctrl: Address 01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
External Reference Frequency Divider Control (RFD) (Refclk_ctrl: Address 04h) . . . . . . . . . . . . . . . . . . . . . . . . .46
Master IC Reset (Mastreset: Address 05h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
IC Electronic ID (Chipcode: Address 06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
IC Revision Code (Revcode: Address 07h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Built In Self-Test (BIST) Receiver Main Control Register (BISTrx_ctrl: Address 11h) . . . . . . . . . . . . . . . . . . . . . .47
Built In Self-Test (BIST) Receiver Bit Error Counter (BISTrx_error: Address 12h) . . . . . . . . . . . . . . . . . . . . . . . . .47
(BISTtx_LOLctrl: Address 17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Mindspeed Proprietary and Confidential
Mindspeed Technologies
®
List of Tables
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