MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 115

• Manufacturer Part Number: MC68HC908QY2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

MOTOROLA
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
the PTA0 pin. A level-shifting and multiplexing interface is required
between PTA0 and the host computer. PTA0 is used in a wired-OR
configuration and requires a pullup resistor.
The monitor code has been updated from previous versions of the
monitor code to allow enabling the internal oscillator to generate the
internal clock. This addition, which is enabled when IRQ is held low out
of reset, is intended to support serial communication/programming at
9600 baud in monitor mode by using the internal oscillator, and the
internal oscillator user trim value OSCTRIM (FLASH location $FFC0, if
programmed) to generate the desired internal frequency (3.2 MHz).
Since this feature is enabled only when IRQ is held low out of reset, it
cannot be used when the reset vector is programmed (i.e., the value is
not $FFFF) because entry into monitor mode in this case requires V
on IRQ. The IRQ pin must remain low during this monitor session in
order to maintain communication.
Table 9-1
specified in the table, monitor mode may be entered after a power-on
reset (POR) and will allow communication at 9600 baud provided one of
the following sets of conditions is met:
•
•
•
If $FFFE and $FFFF does not contain $FF (programmed state):
– The external clock is 9.8304 MHz
– IRQ = V
If $FFFE and $FFFF contain $FF (erased state):
– The external clock is 9.8304 MHz
– IRQ = V
If $FFFE and $FFFF contain $FF (erased state):
– IRQ = V
pullup)
required)
shows the pin conditions for entering monitor mode. As
Monitor ROM (MON)
DD
TST
SS
(internal oscillator is selected, no external clock
(this can be implemented through the internal IRQ
Functional Description
Monitor ROM (MON)
TST
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