MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 93

• Manufacturer Part Number: MC68HC908QY2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

7.7.5 Status Flag Protection in Break Mode
7.8 Low-Power Modes
7.8.1 Wait Mode
MOTOROLA
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The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the break flag control register (BFCR).
Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.
Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a two-step clearing mechanism — for example, a read
of one register followed by the read or write of another — are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the flag
as normal.
Executing the WAIT or STOP instruction puts the MCU in a low
power-consumption mode for standby situations. The SIM holds the
CPU in a non-clocked state. The operation of each of these modes is
described below. Both STOP and WAIT clear the interrupt mask (I) in the
condition code register, allowing interrupts to occur.
In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run.
ADDRESS BUS
DATA BUS
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
System Integration Module (SIM)
WAIT ADDR
last instruction.
Figure 7-15
Figure 7-15. Wait Mode Entry Timing
PREVIOUS DATA
WAIT ADDR + 1
shows the timing for wait mode entry.
NEXT OPCODE
System Integration Module (SIM)
SAME
SAME
Low-Power Modes
SAME
SAME
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