MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 204

• Manufacturer Part Number: MC68HC908QY2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Break Module (BREAK)
17.4.1 Flag Protection During Break Interrupts
17.4.2 CPU During Break Interrupts
17.4.3 TIM During Break Interrupts
17.4.4 COP During Break Interrupts
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The system integration module (SIM) controls whether or not module
status bits can be cleared during the break state. The BCFE bit in the
break flag control register (BFCR) enables software to clear status bits
during the break state. See
Break Interrupts subsection for each module.
The CPU starts a break interrupt by:
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
A break interrupt stops the timer counter.
The COP is disabled during a break interrupt with monitor mode when
BDCOP bit is set in break auxiliary register (BRKAR).
•
•
Loading the instruction register with the SWI instruction
Loading the program counter with $FFFC:$FFFD ($FEFC:$FEFD
in monitor mode)
Break Module (BREAK)
7.9.2 Break Flag Control Register
MOTOROLA
and the