MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 128

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MC68HC908QY2

Manufacturer Part Number
MC68HC908QY2
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet

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Monitor ROM (MON)
128
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
NOTE:
Upon power-on reset, if the received bytes of the security code do not
match the data at locations $FFF6–$FFFD, the host fails to bypass the
security feature. The MCU remains in monitor mode, but reading a
FLASH location returns an invalid value and trying to execute code from
FLASH causes an illegal address reset. After receiving the eight security
bytes from the host, the MCU transmits a break character, signifying that
it is ready to receive a command.
The MCU does not transmit a break character until after the host sends
the eight security bytes.
To determine whether the security code entered is correct, check to see
if bit 6 of RAM address $80 is set. If it is, then the correct security code
has been entered and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on
reset and brought up in monitor mode to attempt another entry. After
failing the security sequence, the FLASH module can also be mass
erased by executing an erase routine that was downloaded into internal
RAM. The mass erase operation clears the security code locations so
that all eight security bytes become $FF (blank).
V
RST
PA0
Notes:
DD
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.
256 BUS CYCLES
FROM HOST
Figure 9-10. Monitor Mode Entry Timing
(MINIMUM)
Monitor ROM (MON)
4096 + 32 CGMXCLK CYCLES
FROM MCU
1
4
1
1
2
4
MOTOROLA
1

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