MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 83

• Manufacturer Part Number: MC68HC908QY2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

7.5.2.2 Computer Operating Properly (COP) Reset
MOTOROLA
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
ADDRESS BUS
BUSCLKX4
BUSCLKX2
PORRST
OSC1
RST
An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.
To prevent a COP module time out, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and stages 12–5 of the
SIM counter. The SIM counter output, which occurs at least every
(2
be serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first time out.
The COP module is disabled during a break interrupt with monitor mode
when BDCOP bit is set in break auxiliary register (BRKAR).
12
CYCLES
4096
– 2
4
) BUSCLKX4 cycles, drives the COP counter. The COP should
Figure 7-7. POR Recovery
System Integration Module (SIM)
CYCLES
32
CYCLES
32
$FFFE
System Integration Module (SIM)
Reset and System Initialization
$FFFF
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