MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 94

• Manufacturer Part Number: MC68HC908QY2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

System Integration Module (SIM)
94
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in
wait mode. Some modules can be programmed to be active in wait
mode.
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the break
status register (BSR). If the COP disable bit, COPD, in the configuration
register is logic 0, then the computer operating properly module (COP)
is enabled and remains active in wait mode.
Figure 7-16
EXITSTOPWAIT
NOTE: EXITSTOPWAIT =
ADDRESS BUS
ADDRESS BUS
BUSCLKX4
DATA BUS
DATA BUS
RST
Figure 7-16. Wait Recovery from Interrupt or Break
System Integration Module (SIM)
Figure 7-17. Wait Recovery from Internal Reset
$A6
$A6
and
Figure 7-17
$6E0B
$A6
$6E0B
$A6
RST
pin OR CPU interrupt OR break interrupt
$A6
$A6
show the timing for wait recovery.
CYCLES
$6E0C
32
$01
$00FF
CYCLES
$0B
32
$00FE
$6E
RST VCT H
$00FD
RST VCT L
MOTOROLA
$00FC