MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 88
MC68HC908QY2
Manufacturer Part Number
MC68HC908QY2
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908QY2.pdf
(230 pages)
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System Integration Module (SIM)
7.7.1.1 Hardware Interrupts
88
ADDRESS BUS
ADDRESS BUS
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
INTERRUPT
INTERRUPT
DATA BUS
DATA BUS
MODULE
MODULE
I BIT
I BIT
R/W
R/W
DUMMY
DUMMY
A hardware interrupt does not stop the current instruction. Processing of
a hardware interrupt begins after completion of the current instruction.
When the current instruction is complete, the SIM checks all pending
hardware interrupts. If interrupts are not masked (I bit clear in the
condition code register), and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.
If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first.
demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.
SP – 4
SP
PC – 1[7:0] PC – 1[15:8]
CCR
Figure 7-10. Interrupt Recovery
Figure 7-9
System Integration Module (SIM)
SP – 1
SP – 3
A
SP – 2
SP – 2
.
Interrupt Entry
X
X
SP – 3
SP – 1
PC – 1[7:0] PC – 1[15:8] OPCODE
A
SP – 4
SP
CCR
VECT H
PC
V DATA H
VECT L
PC + 1
V DATA L
OPERAND
START ADDR
Figure 7-11
OPCODE
MOTOROLA
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