MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 146

• Manufacturer Part Number: MC68HC908QY2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Timer Interface Module (TIM)
146
MC68HC908QY4•MC68HC908QT4•MC68HC908QY2•MC68HC908QT2•MC68HC908QY1•MC68HC908QT1
NOTE:
CHxIE — Channel x Interrupt Enable Bit
MSxB — Mode Select Bit B
MSxA — Mode Select Bit A
Before changing a channel function by writing to the MSxB or MSxA bit,
set the TSTOP and TRST bits in the TIM status and control register
(TSC).
Clear CHxF by reading the TIM channel x status and control register
with CHxF set and then writing a logic 0 to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic 0 to CHxF has no effect. Therefore, an interrupt request cannot
be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.
This read/write bit enables TIM CPU interrupt service requests on
channel x. Reset clears the CHxIE bit.
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM channel 0 status and control register.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.
Reset clears the MSxB bit.
When ELSxB:A
operation or unbuffered output compare/PWM operation.
See
When ELSxB:A = 00, this read/write bit selects the initial output level
of the TCHx pin (see
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
1 = Unbuffered output compare/PWM operation
0 = Input capture operation
1 = Initial output level low
0 = Initial output level high
Table
Timer Interface Module (TIM)
10-3.
00, this read/write bit selects either input capture
Table
10-3). Reset clears the MSxA bit.
MOTOROLA