MC68HC908QY2 MOTOROLA [Motorola, Inc], MC68HC908QY2 Datasheet - Page 154

• Manufacturer Part Number: MC68HC908QY2
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Analog-to-Digital Converter (ADC)
11.4.1 ADC Port I/O Pins
11.4.2 Voltage Conversion
11.4.3 Conversion Time
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NOTE:
PTA0, PTA1, PTA4, and PTA5 are general-purpose I/O pins that are
shared with the ADC channels. The channel select bits (ADC status and
control register (ADSCR), $003C), define which ADC channel/port pin
will be used as the input signal. The ADC overrides the port I/O logic by
forcing that pin as input to the ADC. The remaining ADC channels/port
pins are controlled by the port I/O logic and can be used as
general-purpose I/O. Writes to the port register or data direction register
(DDR) will not have any affect on the port pin that is selected by the ADC.
Read of a port pin which is in use by the ADC will return a logic 0 if the
corresponding DDR bit is at logic 0. If the DDR bit is at logic 1, the value
in the port data latch is read.
When the input voltage to the ADC equals V
signal to $FF (full scale). If the input voltage equals V
converts it to $00. Input voltages between V
straight-line linear conversion. All other input voltages will result in $FF
if greater than V
Input voltage should not exceed the analog supply voltages.
Sixteen ADC internal clocks are required to perform one conversion. The
ADC starts a conversion on the first rising edge of the ADC internal clock
immediately following a write to the ADSCR. If the ADC internal clock is
selected to run at 1 MHz, then one conversion will take 16 s to
complete. With a 1-MHz ADC internal clock the maximum sample rate
is 62.5 kHz.
Number of Bus Cycles = Conversion Time
Conversion Time =
Analog-to-Digital Converter (ADC)
DD
and $00 if less than V
ADC Clock Frequency
16 ADC Clock Cycles
SS
.
DD
DD
, the ADC converts the
and V
Bus Frequency
SS
SS,
are a
the ADC
MOTOROLA