AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 117

• Manufacturer Part Number: AT91RM9200-QU-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QU-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91Rx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, UART, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 122
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 122
• Interface: EBI/EMI, UART/USART
• Ios: 122
• Memory Type: ROM
• Number Of Bits: 32
• Package Type: 208-pin PQFP
• Programmable Memory: 128K Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.65-1.95 V
• Cpu Family: 91R
• Device Core: ARM920T
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 16KB
• # I/os (max): 122
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15. AT91RM9200 Reset Controller
15.1
15.1.1
15.1.1.1
1768I–ATARM–09-Jul-09
Overview
Reset Conditions
NRST Conditions
This chapter describes the AT91RM9200 reset signals and how to use them in order to assure
correct operation of the device.
The AT91RM9200 has two reset input lines called NRST and NTRST. Each line provides,
respectively:
The NRST signal must be considered as the System Reset signal and the reader must take care
when designing the logic to drive this reset signal. NTRST is typically used by the hardware
debug interface which uses the In-Circuit Emulator unit and Initializes it without affecting the nor-
mal operation of the ARM
Both NRST and NTRST are active low signals that asynchronously reset the logic in the
AT91RM92000.
NRST is the active low reset input. When power is first applied to the system, a power-on reset
(also denominated as “cold” reset) must be applied to the AT91RM9200. During this transient
state, it is mandatory to hold the reset signal low long enough for the power supply to reach a
working nominal level and for the oscillator to reach a stable operating frequency. Typically,
these features are provided by every power supply supervisor which, under a threshold voltage
limit, the electrical environment is considered as not nominal. Power-up is not the only event to
be considered as power-down or a brownout are also occurrences that assert the NRST signal.
The threshold voltage must be selected according to the minimum operating voltage of the
AT91RM9200 power supply lines marked as VDD in
acteristics” on page 632.)
The choice of the reset holding delay depends on the start-up time of the low frequency oscilla-
tor as shown below in
page 633.)
Figure 15-1. Cold Reset and Oscillator Start-up relationship
• Initialization of the User Interface registers (defined in the user interface of each peripheral)
• Initialization of the embedded ICE TAP controller.
XIN32
NRST
V
and:
DD
– Sample the signals needed at bootup
– Compel the processor to fetch the next instruction at address zero.
(1)
V
DD(min)
Oscillator Stabilization
after Power-Up
Figure
®
processor. This line shall also be driven by an on board logic.
15-1.
(See Section 37.4.1 ”32 kHz Oscillator Characteristics” on
Figure
15-1.
(See Section 37.2 ”DC Char-
AT91RM9200
117