AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 685

• Manufacturer Part Number: AT91RM9200-QU-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QU-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91Rx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, UART, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 122
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 122
• Interface: EBI/EMI, UART/USART
• Ios: 122
• Memory Type: ROM
• Number Of Bits: 32
• Package Type: 208-pin PQFP
• Programmable Memory: 128K Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.65-1.95 V
• Cpu Family: 91R
• Device Core: ARM920T
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 16KB
• # I/os (max): 122
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

42. Revision History
Revision History
Version A
Version B
1768I–ATARM–09-Jul-09
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Version B Changes Since Last Issue
New Figure 8, ARM920T Internal Functional Block Diagram.
Corrected fields in CP15 Register 7 register table.
Updated Figure 9, AT91RM9200 Debug and Test Block Diagram with corrected DTXD and DRXD signal names and
transfer direction of signals TST0 - TST1 and NRST.
Change signal name to NPCS0.
Changes to Figure 15, Boot Program Algorithm Flow Diagram.
Corrected BMS state to high during reset. Corrected address for internal ROM mapping.
In Table 21 and text, corrected device names AT45DBxxx.
Changes to Figure 20, Serial DataFlash Download.
Updated Table 24 with new pins used and table note.
Code change in section Description of the SvcXmodem Structure.
Code change in Table 29: Xmodem Service, first table cell.
Code change in section Using the Service.
Code change in Table 30: DataFlash Service Methods, first table cell.
Code change in Steps 1 and 2 in section Using the Service.
Changed Table 58, I/O Line Description.
In AIC Source Mode Register, corrected descriptions of bits PRIOR and SRCTYPE.
Change number of programmable clocks to four. Correct oscillator speed to read 32.768 kHz.
Updated section I/O Lines with new information on clocks.
New PMC Block Diagram, Figure 117.
Updated Processor Clock and Programmable Clock Outputs descriptions. Updated Clock Generator description.
New Clock Generator Block Diagram, Figure 118. Section Slow Clock Oscillator Startup Time updated.
Added section Main Oscillator Bypass.
Updated section PLLB Divider by 2.
In section Master Clock Controller, changed references to PLLB Output to PLLB Clock. New Figure 124: Master
Clock Controller. In section Processor Clock Source, specified differences between ARM7-based and ARM9-based
systems.
Section Programmable Clock Output Controller updated to show change in number of programmable clocks.
In Table 60: Clock Switching Timings (Worst Case), changed PLLA Output to PLLA Clock and PLLB Output to PLLB
Clock.
In Figure 125: Switch Master Clock from Slow Clock to PLLA Clock and in Figure 126: Switch Master Clock from
Main Clock to Slow Clock, changed signal names and waveform labels.
In Figure 127: Change PLLA Programming, changed signal names and labels. New Figure 128: Programmable
Clock Output Programming.
Publication Date: 22-Apr-03
Publication Date: 22-Aug-03
AT91RM9200
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