AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 678

• Manufacturer Part Number: AT91RM9200-QU-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QU-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91Rx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, UART, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 122
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 122
• Interface: EBI/EMI, UART/USART
• Ios: 122
• Memory Type: ROM
• Number Of Bits: 32
• Package Type: 208-pin PQFP
• Programmable Memory: 128K Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.65-1.95 V
• Cpu Family: 91R
• Device Core: ARM920T
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 16KB
• # I/os (max): 122
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

41.11 SSC
41.11.1
41.11.2
41.11.3
41.11.4
41.11.5
678
AT91RM9200
Receiver does not take into account a start condition while receiving data
RXSYN and TXSYN not cleared when read
Receiver Speed Limitations
Transmitter Speed Limitations
Disabling the SSC does not stop the Frame Synchronization signal generation
The SSC receiver does not support reception of the last data sequence of a frame that overlaps
a new start of frame, regardless of the mode of detection of the start condition. For example, this
prevents reception of the last data of a TDM bus.
Problem Fix/Workaround
None.
The status bits RXSYN and TXSYN are active during a complete serial clock period and are not
immediately cleared when SSC_SR is read.
Problem Fix/Workaround
The user must enable the interrupt relevant to RXSYN and TXSYN.
Problem Fix/Workaround
None.
Problem Fix/Workaround
None.
Generating RF can be stopped only by programming the FSOS field in SSC_RFMR to 0x0.
Generating TF can be stopped only by programming the FSOS field in SSC_TFMR to 0x0.
Problem Fix/Workaround
None.
– If RF is programmed as input, the maximum clock frequency is MCK divided by 2.
– If RF is programmed as output and RK is programmed as input, the maximum clock
– If RF and RK are both programmed as output, the maximum clock frequency is MCK
– If both TF and TK are programmed as output, the maximum clock frequency is MCK
– If TF is programmed in output and TK is programmed as input, the maximum clock
– If both TF and TK are programmed as input, the maximum clock frequency is MCK
– If TF is programmed in input and TK is programmed as output, the maximum clock
frequency is MCK divided by 6.
divided by 4.
divided by 4.
frequency is MCK divided by 8.
divided by 8.
frequency is MCK divided by 4.
1768I–ATARM–09-Jul-09