AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 680

• Manufacturer Part Number: AT91RM9200-QU-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QU-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91Rx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, UART, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 122
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 122
• Interface: EBI/EMI, UART/USART
• Ios: 122
• Memory Type: ROM
• Number Of Bits: 32
• Package Type: 208-pin PQFP
• Programmable Memory: 128K Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.65-1.95 V
• Cpu Family: 91R
• Device Core: ARM920T
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 16KB
• # I/os (max): 122
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

41.12.4
41.12.5
41.12.6
41.12.7
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41.12.9
680
AT91RM9200
Bad capture at restart if burst low
TIOA and TIOB outputs stuck in case of simultaneous events
TIMER_CLOCK2 not sampled on same edge as TIMER_CLOCK0 and TIMER_CLOCK1
Triggers do not clear the counter in Up/Down Mode
Triggers in Up/Down Mode are lost when burst signal is active
Clock Selection Limitation in Up/Down Mode
The captured value is not zero if burst is low when the preceding trigger event is recognized.
Instead, the captured value is the Counter Value before the trigger.
Problem Fix/Workaround
None.
In the register TC_CMR, if at least one of the fields ASWTRG or AEEVT or ACPC is set to 0x0
(none), the event programmed by ACPA is not carried out.
In the register TC_CMR, if at least one of the fields ASWTRG or AEEVT is set to 0x0 (none), the
event programmed by ACPC is not carried out.
In the register TC_CMR, if the field ASWTRG is set to 0x0 (none), the event programmed by
AEEVT is not carried out.
The same problem exists on the TIOB output with the fields BSWTRG, BEEVT, BCPC and
BCPB.
Problem Fix/Workaround
An order of priority for TIOA and/or TIOB events must be defined depending on the user
application.
TIMER_CLOCK2/TIMER_CLOCK5 is sampled on the system clock falling edge of Master Clock,
whereas TIMER_CLOCK0/TIMER_CLOCK3 and TIMER_CLOCK1/TIMER_CLOCK4 are sam-
pled on the rising edge of Master Clock. This should not have any effect on the functional
operations of the Timer Counter unless the Timer Counter is used at its speed limit.
Problem Fix/Workaround
None.
When the field WAVESEL in TC_CMR is at value 0x1 or 0x3, the triggers do not reset the coun-
ter value. The counter value can be reset only by modifying the field WAVESEL.
Problem Fix/Workaround
None.
When the field WAVESEL in TC_CMR is at value 0x1 or 0x3, the triggers occurring while the
selected burst signal is active (clock disabled) are not taken into account.
Problem Fix/Workaround
None.
Selecting the Master Clock or the Master Clock divided by 2 as the Timer Counter Clock may
lead to unpredictable result when the field WAVESEL in TC_CMR is at value 0x1 or 0x3.
Problem Fix/Workaround
1768I–ATARM–09-Jul-09