AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 45

• Manufacturer Part Number: AT91RM9200-QU-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QU-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91Rx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, UART, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 122
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 122
• Interface: EBI/EMI, UART/USART
• Ios: 122
• Memory Type: ROM
• Number Of Bits: 32
• Package Type: 208-pin PQFP
• Programmable Memory: 128K Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.65-1.95 V
• Cpu Family: 91R
• Device Core: ARM920T
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 16KB
• # I/os (max): 122
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Write-back Operation
11.6.2.2
11.6.2.3
1768I–ATARM–09-Jul-09
Write Buffer
Physical Address Tag RAM (PA TAG RAM)
When a cache hit occurs for a data access, the cache line is marked as dirty, meaning that its
contents are not up-to-date with those in the main memory.
The ARM920T incorporates a 16-entry write buffer to avoid stalling the processor when writes to
external memory are performed. When a store occurs, its data, address and other details are
written to the write buffer at high speed. The write buffer then completes the store at the main
memory speed (typically slower than the ARM speed). In parallel, the ARM9TDMI processor can
execute further instructions at full speed.
The ARM920T implements Physical Address Tag RAM (PA TAG RAM) to perform write-backs
from the data cache. The physical address of all the lines held in the data cache is stored in the
PA TAG memory, removing the need for address translation when evicting a line from the cache.
When a line is written into the data cache, the physical address TAG is written into the PA TAG
RAM. If this line has to be written back to the main memory, the PA TAG RAM is read and the
physical address is used by the AMBA ASB interface to perform the write-back.
For a 16-Kbyte DCache, the PA TAG RAM is organized by eight segments with:
• 64 rows per segments
• 26 bits per rows
• be
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