AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 222

• Manufacturer Part Number: AT91RM9200-QU-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QU-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91Rx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, UART, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 122
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 122
• Interface: EBI/EMI, UART/USART
• Ios: 122
• Memory Type: ROM
• Number Of Bits: 32
• Package Type: 208-pin PQFP
• Programmable Memory: 128K Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.65-1.95 V
• Cpu Family: 91R
• Device Core: ARM920T
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 16KB
• # I/os (max): 122
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 20-6. Burst Suspend and Resume with Signal Control Address Advance
222
Selection Signal
Internal BFC
AT91RM9200
BFAVD
BFBAA
A[24:0]
D[15:0]
D[15:0]
Output
BFWE
BFOE
BFCS
BFCK
Input
Burst Suspend and Resume (BFOEH = 1)
Signal Control Address Advance (BAAEN = 1)
(1) Only if Multiplexed Address & Data Buses
These protocols are illustrated in
Valid Latency AVL+1
ber of cycles from the first rising clock edge when BFAVD is asserted to the rising edge that
causes the read of data D1.
Note:
Address (1)
2. In case of sequential access, and provided that the BFOEH mode is selected in the
Address (D0)
This new address is registered in the BFC and is then used as reference for further
accesses.
mode register
burst address is incremented:
– Through the BFBAA pin, if the Signal Controlled Address Advance is enabled.
– By enabling the clock during one clock cycle in Clock Controlled Address Advance
Mode.
This rising edge is also used to latch D0 in the BFC.
AVL
See “Burst Flash Controller Mode Register” on page
See “Burst Flash Controller Mode Register” on page 227.
Sampling
D0
D0
Sampling
D1
D1
Figure 20-6
Sampling
D2
D2
Sampling
D3
D3
Address Valid Latency = 4 BFCK cycles (AVL field = 3)
Output Enable Latency (OEL) = 2 BFCK cycles
below and
D4
Burst Suspend
Figure 20-7 on page
OEL = 2
Sampling
227., the internal
Burst Resume
D4
D4
1768I–ATARM–09-Jul-09
223. The Address
Sampling
D5
gives the num-
D5
D6