AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 53

• Manufacturer Part Number: AT91RM9200-QU-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QU-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91Rx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, UART, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 122
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 122
• Interface: EBI/EMI, UART/USART
• Ios: 122
• Memory Type: ROM
• Number Of Bits: 32
• Package Type: 208-pin PQFP
• Programmable Memory: 128K Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.65-1.95 V
• Cpu Family: 91R
• Device Core: ARM920T
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 16KB
• # I/os (max): 122
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Function Details
Stops execution in low-power state until an interrupt occurs.
The cache line (or lines) is marked as invalid, so no cache hits occur in that line until it is re-allocated to an address.
Applies to write-back data caches. If the cache line contains stored data that has not yet been written out to the main mem-
ory, it is written to main memory immediately.
Stops the execution until all data in the write buffer has been stored in the main memory.
The memory cache line at the specified virtual address is loaded into the cache.
The operation carried out on a single cache line identifies the line using the data transferred in the MCR instruction.
The data is interpreted as using one of the two formats:
Below are the details of CP15 Register 7, or Cache Function Register, in MVA format.
• mva[31:5]: Modified Virtual Address
The non-defined bits should be zero when written and are unpredictable when read.
1768I–ATARM–09-Jul-09
• Wait for interrupt
• Invalidate
• Clean
• Drain write buffer
• Prefetch
– MVA format
– index format
31
23
15
7
mva
30
22
14
6
29
21
13
5
28
20
12
4
-
mva
mva
mva
27
19
11
3
-
26
18
10
2
-
AT91RM9200
25
17
9
1
-
24
16
8
0
-
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