AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 43
![IC ARM9 MCU 208 PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT91RM9200-QU-002
Manufacturer Part Number
AT91RM9200-QU-002
Description
IC ARM9 MCU 208 PQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets
1.AT91RM9200-EK.pdf
(41 pages)
2.AT91RM9200-QU-002.pdf
(701 pages)
3.AT91RM9200-QU-002.pdf
(38 pages)
Specifications of AT91RM9200-QU-002
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR
Number Of I /o
122
Program Memory Size
128KB (128K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Processor Series
AT91Rx
Core
ARM7TDMI
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, EBI, I2S, SPI, UART, USART
Maximum Clock Frequency
180 MHz
Number Of Programmable I/os
122
Number Of Timers
10 bit
Operating Supply Voltage
3 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
Minimum Operating Temperature
- 40 C
Eeprom Memory
0 Bytes
Input Output
122
Interface
EBI/EMI, UART/USART
Ios
122
Memory Type
ROM
Number Of Bits
32
Package Type
208-pin PQFP
Programmable Memory
128K Bytes
Timers
3-16-bit
Voltage, Range
1.65-1.95 V
Cpu Family
91R
Device Core
ARM920T
Device Core Size
32b
Frequency (max)
180MHz
Total Internal Ram Size
16KB
# I/os (max)
122
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
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11.5
11.5.1
11.5.2
1768I–ATARM–09-Jul-09
Memory Management Unit (MMU)
Domain
MMU Faults
The ARM920T processor implements an enhanced ARM architecture v4 MMU to provide trans-
lation and access permission checks for the instruction and data address ports of the
ARM9TDMI core. The MMU is controlled from a single set of two-level page tables stored in the
main memory, providing a single address and translation protection scheme. Independently,
instruction and data TLBs in the MMU can be locked and flushed.
Table 11-5.
A domain is a collection of sections and pages. The ARM920T supports 16 domains. Access to
the domains is controlled by the Domain Access Control register. For details, refer to
Register 3, Domain Access Control Register” on page
The MMU generates alignment faults, translation faults, domain faults and permission faults.
Alignment fault checking is not affected by whether the MMU is enabled or not.
The access controls of the MMU detect the conditions that produce these faults. If the fault is a
result of memory access, the MMU aborts the access and signals the fault to the CPU core.The
MMU stores the status and address fault in the FSR and FAR registers (only for faults generated
by data access).
The MMU does not store fault information about faults generated by an instruction fetch.
The memory system can abort during line fetches, memory accesses and translation table
access.
Mapping Name
Section
Large Page
Small Page
Tiny Page
Mapping Details
Mapping Size
1M byte
64K bytes
4K bytes
1K byte
Access Permission By
4 separated subpages
Section
4 separated subpages
Tiny Page
50.
Subpage Size
-
16K bytes
1K byte
-
AT91RM9200
“CP15
43
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