AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 41

• Manufacturer Part Number: AT91RM9200-QU-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QU-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91Rx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, UART, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 122
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 122
• Interface: EBI/EMI, UART/USART
• Ios: 122
• Memory Type: ROM
• Number Of Bits: 32
• Package Type: 208-pin PQFP
• Programmable Memory: 128K Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.65-1.95 V
• Cpu Family: 91R
• Device Core: ARM920T
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 16KB
• # I/os (max): 122
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.4
11.4.1
CP15 registers can only be accessed in privileged mode by:
Other instructions (CDP, LDC, STC) cause an undefined instruction exception.
The MCR instruction is used to write an ARM register to CP15.
The MRC instruction is used to read the value of CP15 to an ARM register.
The assembler code for these instructions is:
1768I–ATARM–09-Jul-09
MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2.
CP15 Coprocessor
CP15 Register Access
Coprocessor 15, or System Control Coprocessor CP15, is used when special features are used
with the ARM9TDMI such as:
To control these features, CP15 provides 16 additional registers. See
Table 11-4.
Notes:
• On-chip Memory Management Unit (MMU)
• Instruction and/or Data Cache
• Write buffer
• MCR (Move to Coprocessor from ARM Register) instruction
• MRC (Move to ARM Register from Coprocessor) instruction
Register
1. TLB: Translation Lookaside Buffer
2. FCSE PID: Fast Context Switch Extension Process Identifier
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
CP15 Registers
Name
ID Register
Control
Translation Table Base
Domain Access Control
Reserved
Fault Status
Fault Address
Cache Operations
TLB
cache lockdown
TLB lockdown
Reserved
Reserved
FCSE PID
Reserved
Test configuration
(1)
Operations
(2)
Read-only
Read/Write
Read/Write
Read/Write
None
Read/Write
Read/Write
Write-only
Read/Write
Read/Write
None
None
Read/Write
None
None
Access
Write-only
Table
AT91RM9200
11-4.
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