AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 57

• Manufacturer Part Number: AT91RM9200-QU-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QU-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91Rx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, UART, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 122
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 122
• Interface: EBI/EMI, UART/USART
• Ios: 122
• Memory Type: ROM
• Number Of Bits: 32
• Package Type: 208-pin PQFP
• Programmable Memory: 128K Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.65-1.95 V
• Cpu Family: 91R
• Device Core: ARM920T
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 16KB
• # I/os (max): 122
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.7.11
Access: Read/Write
The CP15 Register 10, or TLB Lockdown Register, is 0x0 on reset. There is a TLSB Lockdown Register for each of the
TLBs; the value of opcode_2 determines which TLB register to access:
Table 11-9.
• Base[31:26]: Base
The TLB replacement strategy only uses the TLB entries numbered from base to 63. The Victim field provided is in that
range.
• Victim[25:20]: Victim Counter
Specifies the TLB entry (line) being overwritten.
• P[0]: Preserved
If 0, the TLB entry can be invalidated.
If 1, the TLB entry is protected. It cannot be invalidated during the Invalidate All instruction. Refer to
Operations Register” on page
The non-defined bits should be zero when written and are unpredictable when read.
11.7.12
Any access (Read or Write) to these registers causes unpredictable behavior.
1768I–ATARM–09-Jul-09
Function
Read D TLB lockdown
Write D TLB lockdown
Read I TLB lockdown
Write I TLB lockdown
• opcode_2 = 0x0 for D TLB register
• opcode_2 = 0x1 for I TLB register
31
23
15
7
-
-
CP15 Register 10, TLB Lockdown Register
CP15 Registers 11, 12, Reserved
TLB Lockdown Functions
30
22
14
6
-
-
Victim
55.
29
21
13
5
-
-
Base
28
20
12
4
-
-
TLB lockdown
TLB lockdown
TLB lockdown
TLB lockdown
27
19
11
3
-
-
-
Data
26
18
10
2
-
-
-
CRm
0
0
0
0
AT91RM9200
25
17
9
1
-
-
-
“CP15 Register 8, TLB
Opcode_2
0
0
1
1
24
16
P
8
0
-
-
D
57