AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 118

• Manufacturer Part Number: AT91RM9200-QU-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QU-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91Rx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, UART, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 122
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 122
• Interface: EBI/EMI, UART/USART
• Ios: 122
• Memory Type: ROM
• Number Of Bits: 32
• Package Type: 208-pin PQFP
• Programmable Memory: 128K Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.65-1.95 V
• Cpu Family: 91R
• Device Core: ARM920T
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 16KB
• # I/os (max): 122
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.1.1.2
15.1.2
15.1.2.1
15.1.2.2
118
AT91RM9200
Reset Management
NTRST Assertion
System Reset
Test Access Port (TAP) Reset
Note:
NRST can also be asserted in circumstances other than the power-up sequence, such as a
manual command. This assertion can be performed asynchronously, but exit from reset is syn-
chronized internally to the default active clock. During normal operation, NRST must be active
for a minimum delay time to ensure correct behavior. See
Table 15-1.
Figure 15-2. NRST assertion
As with the NRST signal, at power-up, the NTRST signal must be valid while the power supply
has not obtained the minimum recommended working level. A clock on TCK is not required to
validate this reset request.
As with the NRST signal, NTRST can also be asserted in circumstances other than the power-
up sequence, such as a manual command or an ICE Interface action. This assertion and de-
assertion can be performed asynchronously but must be active for a minimum delay time.
Section 38.3 ”JTAG/ICE Timings” on page 657.)
The system reset functionality is provided through the NRST signal.
This Reset signal is used to compel the microcontroller unit to assume a set of initial conditions:
With the exception of the program counter and the Current Program Status Register, the proces-
sor’s registers do not have defined reset states. When the microcontroller’s NRST input is
asserted, the processor immediately stops execution of the current instruction independently of
the clock.
The system reset circuitry must take two types of reset requests into account:
Both have the same effect but can have different assertion time requirements regarding the
NRST pin. In fact, the cold reset assertion has to overlap the start-up time of the system. The
user reset request requires a shorter assertion delay time than does cold reset.
Test Access Port (TAP) reset functionality is provided through the NTRST signal.
Symbol
RST1
• Sample the Boot Mode Select (BMS) logical state.
• Restore the default states (default values) of the user interface.
• Require the processor to perform the next instruction fetch from address zero.
• The cold reset needed for the power-up sequence.
• The user reset request.
NRST
1. VDD is applicable to VDD
Parameter
NRST Minimum Pulse Width
Reset Minimum Pulse Width
IOM
, VDD
RST1
Min. Pulse Width
IOP
, VDD
PLL
, VDD
92
Figure 15-2
OSC
and VDD
and
CORE
Table
Unit
1768I–ATARM–09-Jul-09
15-1.
µs
(See