AT91RM9200-QU-002 Atmel, AT91RM9200-QU-002 Datasheet - Page 673

• Manufacturer Part Number: AT91RM9200-QU-002
• Description: IC ARM9 MCU 208 PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91RM9200-QU-002

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR
• Number Of I /o: 122
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Processor Series: AT91Rx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, UART, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 122
• Number Of Timers: 10 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91RM9200-EK
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 122
• Interface: EBI/EMI, UART/USART
• Ios: 122
• Memory Type: ROM
• Number Of Bits: 32
• Package Type: 208-pin PQFP
• Programmable Memory: 128K Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.65-1.95 V
• Cpu Family: 91R
• Device Core: ARM920T
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 16KB
• # I/os (max): 122
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• For Use With: AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

41.4.4
41.4.5
41.4.6
41.4.7
41.4.8
41.4.9
41.4.10
1768I–ATARM–09-Jul-09
STOP during a WRITE_MULTIPLE_BLOCK command
DTIP flag
STOP command with SYNCHRONISED special command
Data FIFO and status bits
DATA FIFO problem with PDC
DATA_CRC_ERR flag never rises
STOP during a READ_MULTIPLE_BLOCK command
Problem Fix/Workaround
None.
The WRITE_MULTIPLE_BLOCK with a transfer size (PDC) not a multiple of the block length is
not stopped by the STOP command.
Problem Fix/Workaround
Choose an appropriate size for the block length.
The DTIP flag is not reset if STOP_COMMAND is received in the middle of a block data transfer.
Problem Fix/Workaround
None.
A STOP command with SYNCHRONISED special command is sent after the block data transfer
ends. During this time the MMCI receives data but the RXRDY flag is no longer asserted.
Problem Fix/Workaround
Do not send a STOP command with SYNCHRONISED special command.
Do not read/write the Data FIFO if RXRDY/TXRDY status bits are not set.
Problem Fix/Workaround
None.
The shared FIFO is reset at the beginning of a transfer command.
Problem Fix/Workaround
So as to avoid losing data, it is mandatory to enable the PDC channel after writing to the com-
mand register. In order to achieve this sequence correctly, it is mandatory to disable all IT
sources.
The DATA_CRC_ERR (error flag) never rises during the checking of bad data CRC status sent
by MMC/SD card after block writing.
Problem Fix/Workaround
CRC must be done by software.
If the user sends a READ_MULTIPLE_BLOCK command and stops it by using a
STOP_COMMAND in the middle of a data block transfer then the internal state of the MMCI
controller stops in a bad state.After that the following read block (with READ_SINGLE_BLOCK
or READ_MULTIPLE_BLOCK) will be entirely corrupted.
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