MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1099
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MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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A.2.9.5
This MPC562/MPC564 instruction is divided into two segments. The left segment is either fully bypassed
by a 16-bit field or by a shorter field which is decompressed according to fixed rules. The right segment
is compressed and mapped into a vocabulary. The vocabulary location is programmable. The compressed
fields must be swapped in the compressed instruction order to follow the rule that bypass appears only in
the second field of a compressed instruction.
The definition of the class includes:
When the vocabulary is located in RAM #1, the class is referred to as CLASS_4band when the vocabulary
is located in RAM #2, the class is referred to as CLASS_4a. Refer to
A.2.10
Table A-4
The un-compressed instruction of two half-words are referred as H1 & H2. The compressed instruction
can be built out of: (1) X1 field – representing a vocabulary pointer for encoding of either H1 or H1+H2;
(2) X2 field – representing a vocabulary pointer for encoding of H2; and (3) BP – representing a bypass
field.
Vocabularies V1 and V2 refer to the 16 MSB and 16 LSB of the uncompressed instruction, respectively.
A.2.11
The compression process is implemented by the following steps. See
Freescale Semiconductor
.
MSB
•
•
•
•
•
•
•
•
•
16-bit segment #1 – to be bypassed
4-bit class
TP1 length=2-9
TP2 length=0xB, 0xC, 0xD, or 0xE indicating a 0, 10, 15 or 16 bit bypass, respectively.
TP1 base address = base address of segment #1 vocabulary in RAM #1, if it exists there
TP2 base address = base address of segment #1 vocabulary in RAM #2, if it exists there
DS=1
AS=0 or 1 directing access to the vocabulary in RAM #1 or RAM #2, respectively.
User code compilation/linking
Vocabulary and class generation
User application code compression by a software compression tool
summarizes the programming for all possible compressed instruction layouts.
Instruction Layout Programming Summary
Compression Process
Left Segment Bypass and Right Segment Compression—CLASS_4
2- to 9-bit TP1 for segment #2
Figure A-10. CLASS_4 Instruction Layout
MPC561/MPC563 Reference Manual, Rev. 1.2
Uncompressed Instruction
Compressed Instruction
16-bit segment #2 – to be compressed
0-, 10-, 15- or 16-bit bypass for segment #1
Table
Figure
MPC562/MPC564 Compression Features
A-4.
A-11.
A-11
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