MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 850
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Time Processor Unit 3
19-20
11:13
Bits
9:10
14
15
8
Filter Control
000
001
010
011
100
SOFT RST Soft reset. The TPU3 performs an internal reset when both the SOFT RST bit in the TPUMCR2
ETBANK
FPSCK
Name
DTPU
T2CF
Table 19-20. System Clock Frequency/Minimum Guaranteed Detected Pulse
and the STOP bit in TPUMCR are set. The CPU must write zero to the SOFT RST bit to bring
the TPU3 out of reset. The SOFT RST bit must be asserted for at least nine clocks.
0 Normal operation
1 Puts TPU3 in reset until bit is cleared
NOTE: Do not attempt to access any other TPU3 registers when this bit is asserted. When this
bit is asserted, it is the only accessible bit in the register.
Entry table bank select. This field determines the bank where the microcoded entry table is
situated. After reset, this field is 0b00. This control bit field is write once after reset. ETBANK is
used when the microcode contains entry tables not located in the default bank 0. To execute the
ROM functions on this MCU, ETBANK[1:0] must be 00. Refer to
NOTE: This field should not be modified by the programmer unless necessary because of custom
microcode.
Filter prescaler clock. The filter prescaler clock control bit field determines the ratio between
system clock frequency and minimum detectable pulses. The reset value of these bits is zero,
defining the filter clock as four system clocks. Refer to
T2CLK pin filter control. When asserted, the T2CLK input pin is filtered with the same filter clock
that is supplied to the channels. This control bit is write once after reset.
0 Uses fixed four-clock filter
1 T2CLK input pin filtered with same filter clock that is supplied to the channels
Disable TPU3 pins. When the disable TPU3 control pin is asserted, pin TP15 is configured as an
input disable pin. When the TP15 pin value is zero, all TPU3 output pins are three-stated,
regardless of the pins function. The input is not synchronized. This control bit is write once after
reset.
0 TP15 functions as normal TPU3 channel
1 TP15 pin configured as output disable pin. When TP15 pin is low, all TPU3 output pins are in
a high-impedance state, regardless of the pin function.
Divide By
Table 19-18. TPUMCR2 Bit Descriptions (continued)
16
32
64
4
8
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 19-19. Entry Table Bank Location
ETBANK
20 MHz
200 ns
400 ns
800 ns
1.6 µs
3.2 µs
00
01
10
11
Description
Bank
33 MHz
1.94 µs
121 ns
242 ns
485 ns
970 ns
0
1
2
3
Table
19-20.
40 MHz
1.60 µs
100 ns
200 ns
400 ns
800 ns
Table
19-19.
Freescale Semiconductor
56 MHz
1.14 µs
143 ns
286 ns
571 ns
71 ns
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