MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 72

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

21-7
21-8
21-9
21-10
22-1
22-2
22-3
22-4
22-5
22-6
22-7
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
23-10
23-11
23-12
23-13
23-14
23-15
23-16
23-17
23-18
23-19
23-20
23-21
23-22
23-23
23-24
23-25
23-26
23-27
23-28
Freescale Semiconductor
Table
Number
Program Interlock State Descriptions ................................................................................... 21-23
Erase Interlock State Descriptions ........................................................................................ 21-27
Censorship States .................................................................................................................. 21-30
Censorship Modes and Censorship Status ............................................................................ 21-31
Priorities of Overlay Regions ............................................................................................... 22-12
CALRAM Control Registers ................................................................................................ 22-13
CRAMMCR Bit Descriptions............................................................................................... 22-14
CRAMMCR Privilege Bit Assignment for 8-Kbyte Array Blocks ...................................... 22-15
CRAM_RBAx Bit Descriptions ........................................................................................... 22-16
RGN_SIZE Encoding ........................................................................................................... 22-16
CRAMOVLCR Bit Descriptions .......................................................................................... 22-17
VF Pins Instruction Encodings ............................................................................................... 23-3
VF Pins Queue Flush Encodings ............................................................................................ 23-3
VFLS Pin Encodings .............................................................................................................. 23-4
Detecting the Trace Buffer Start Point ................................................................................... 23-6
Fetch Show Cycles Control .................................................................................................... 23-7
Instruction Watchpoints Programming Options ................................................................... 23-15
Load/Store Data Events ........................................................................................................ 23-16
Load/Store Watchpoints Programming Options................................................................... 23-17
Check Stop State and Debug Mode ...................................................................................... 23-27
Trap Enable Data Shifted into Development Port Shift Register ......................................... 23-34
Debug Port Command Shifted Into Development Port Shift Register ................................. 23-34
Status / Data Shifted Out of Development Port Shift Register............................................. 23-35
Debug Instructions / Data Shifted into Development Port Shift Register ............................ 23-36
Development Support Programming Model......................................................................... 23-39
Development Support Registers Read Access Protection .................................................... 23-40
Development Support Registers Write Access Protection ................................................... 23-41
CMPA-CMPD Bit Descriptions ........................................................................................... 23-41
ECR Bit Descriptions............................................................................................................ 23-42
DER Bit Descriptions ........................................................................................................... 23-43
Breakpoint Counter A Value and Control Register (COUNTA).......................................... 23-45
CMPE–CMPF Bit Descriptions............................................................................................ 23-46
CMPG-CMPH Bit Descriptions ........................................................................................... 23-47
LCTRL1 Bit Descriptions..................................................................................................... 23-47
LCTRL2 Bit Descriptions..................................................................................................... 23-49
ICTRL Bit Descriptions........................................................................................................ 23-51
ISCT_SER Bit Descriptions ................................................................................................. 23-52
BAR Bit Descriptions ........................................................................................................... 23-53
Breakpoint Counter B Value and Control Register (COUNTB) ......................................... 23-46
MPC561/MPC563 Reference Manual, Rev. 1.2
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