MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 296
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Reset
During the assertion of the PORESET input signal, the chip assumes the default reset configuration. This
assumed configuration changes if the input signal RSTCONF is asserted when the PORESET is negated
or the CLKOUT starts to oscillate. To ensure that stable data is sampled, the hardware configuration is
sampled every eight clock cycles on the rising edge of CLKOUT with a double buffer. The setup time
required for the data bus is approximately 15 cycles (defined as Tsup in the following figures) and the
maximum rise time of HRESET should be less than six clock cycles. In systems where an external reset
configuration word and the TEXP output function are both required, RSTCONF should be asserted until
SRESET is negated.
Figure 7-3
7-8
Reset
Config.
Word
to
Has Configuration (HC)
Figure 7-6
Timing diagrams in the following figures are not to scale.
OE
M U X
INT_RESET
provide sample reset configuration timings.
Figure 7-2. Reset Configuration Basic Scheme
3 2
3 2
MPC561/MPC563 Reference Manual, Rev. 1.2
3 2
Coherency
Data
Flash
NOTE
Dx (Data line)
EXT_RESET
(See
HRESET/SRESET
Table
7-2)
Freescale Semiconductor
RSTCONF
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