MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 895
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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21.3.11.4 Switching The UC3F EEPROM Censorship
There are three states of censorship that CENSOR[0:1] can select. These are—cleared censorship, no
censorship (two states) and information censorship. These three states, state values, transitions, and state
of censorship are shown in
Freescale Semiconductor
5. Read the UC3FCTL register until HVS = 0.
6. Read the UC3FCTL register. Confirm PEGOOD = 1.
7. Write EHV = 0 in the UC3FCTL register.
8. Write SES = 0 and CSC = 0.
T4
Information Censorship
The values of the EPEE and B0EPEE inputs are latched with the assertion
of EHV to determine the array protection state for the clear censor
operation. It is assumed that the EPEE and B0EPEE inputs are setup prior
to the assertion of EHV. If EPEE and B0EPEE are not enabled for erase, the
CENSOR[0:1] bits may not be cleared.
Cleared Censorship
No Censorship
Figure
Figure 21-11. Censorship States and Transitions
MPC561/MPC563 Reference Manual, Rev. 1.2
21-11.
CENSOR[0:1] = 01
T3
Data
Data
Unknown
NOTE
CENSOR[0:1] = 11
CENSOR[0:1] = 00
Data
Data
Data
T2
T1
CENSOR[0:1] = 10
T3
Data
Data
CDR3 Flash (UC3F) EEPROM
T3
21-33
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