MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 816
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
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Peripheral Pin Multiplexing (PPM) Module
SHORT_REG[SH_ET2]. ETRIG1 can be shorted to A_TPUCH15 and ETRIG2 can be shorted to
B_TPUCH15.
Since the ETRIG1 and ETRIG2 signals are shared with PCS6 and PCS7 respectively, the PPM shorting
will allow both ETRIG and PCS functions to be available. By setting up A_TPUCH15 and/or
B_TPUCH15 as output signals, enabling a short to ETRIG1 and/or ETRIG2 and sending a trigger signal
from the TPU channels, the QADC64E can be successfully triggered, leaving the ETRIG signals free to
be configured for PCS functions.
18.3.2.4
Each of the two TPU modules has an input clock, T2CLK. The A_T2CLK and B_T2CLK signals are
shared with PCS4 and PCS5 respectively. The T2CLK signals can be shorted internally by
SHORT_REG[SH_T2CLK] so that only one signal needs to be input to the device, leaving the other signal
free for PCS functionality.
18.3.3
The PPM module has six pads associated with it, four I/O pads PPM_RX[0:1] and PPM_TX[0:1] and two
clock outputs PPM_TCLK and PPM_TSYNC. All six PPM signals are multiplexed with MIOS signals. In
order to be able to access the PPM functions the signals must be configured appropriately. PPM pad control
is done in the PDMCR2 register.
As well as enabling signal functions, this register can configure the PPM pads for 2.6-V or 5-V operation.
Refer to
18.4
18.4.1
18-10
SRESET
Field STOP
Addr
Chapter 2, “Signal
PPM Registers
MSB
PPM Module Pad Configuration
Module Configuration Register (PPMMCR)
T2CLK
0
1
2
Figure 18-8. Module Configuration Register (PPMMCR)
Descriptions,” for more details.
3
RESERVED
MPC561/MPC563 Reference Manual, Rev. 1.2
4
5
0000_0000_0000_0000
6
0x30 5C00
7
SUPV
8
9
10
11
RESERVED
12
Freescale Semiconductor
13
14
LSB
15
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