MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 196
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Central Processing Unit
When a program exception is taken, instruction execution resumes at offset 0x0700 from the physical base
address indicated by MSR[IP].
3.15.4.8
A floating-point unavailable exception occurs when no higher priority exception exists, an attempt is made
to execute a floating-point instruction (including floating-point load, store, and move instructions), and the
floating-point available bit in the MSR is disabled, (MSR[FP] = 0).
3-52
1
2
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Only one of bits 11, 13, and 14 can be set.
Machine State Register (MSR)
Floating-Point Unavailable Exception (0x0800)
Table 3-29. Register Settings following a Floating-Point Unavailable Exception
Register
Register
Table 3-28. Register Settings following Program Exception
1
2
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
[16:31]
[16:31]
[0:10]
Other
[0:15]
Bits
Bits
ME
LE
All
11
12
13
14
15
All
IP
Contains the effective address of the excepting instruction
cleared.
cleared.
causing the exception, and set if SRR0 contains the address of
a subsequent instruction.
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI].
No change
Set to value of ILE bit prior to the exception
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Set to the effective address of the instruction that caused the
exception.
Loaded from MSR[16:31]
Cleared to 0
Set for a floating-point enabled program exception; otherwise
Cleared to 0.
Set for a privileged instruction program exception; otherwise
Set for a trap program exception; otherwise cleared.
Cleared to 0 if SRR0 contains the address of the instruction
No change
Cleared to 0
Cleared to 0
Setting Description
Setting Description
Freescale Semiconductor
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