MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 632
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Serial Multi-Channel Module
15.6
The queued serial peripheral interface (QSPI) is used to communicate with external devices through a
synchronous serial bus. The QSPI is fully compatible with SPI systems found on other Freescale products,
but has enhanced capabilities. The QSPI can perform full duplex three-wire or half duplex two-wire
transfers. Several transfer rates, clocking, and interrupt-driven communication options are available.
Figure 15-10
15-14
Note: See bit descriptions in
SRESET
Bits
Field
Addr
0:7
10
11
12
13
14
15
8
9
Queued Serial Peripheral Interface
MSB
is a block diagram of the QSPI.
0
QDDPCS3
QDDPCS2
QDDPCS1
QDDPCS0
QPDMOSI
QPDMISO
QDDSCK
PQSPAR
Name
1
—
PQSPAR*
2
3
Figure 15-9. PORTQS Data Direction Register (DDRQS)
Table 15-10
4
PORTSQS pin assignment register. See
Register
Reserved
QSPI pin data direction for the pin PCS3
0 Pin direction is input
1 Pin direction is output
QSPI pin data direction for the pin PCS2
0 Pin direction is input
1 Pin direction is output
QSPI pin data direction for the pin PCS1
0 Pin direction is input
1 Pin direction is output
QSPI pin data direction for the pin PCS0
0 Pin direction is input
1 Pin direction is output
QSPI pin data direction for the pin SCK
0 Pin direction is input
1 Pin direction is output
QSPI pin data direction for the pin MOSI
0 Pin direction is input
1 Pin direction is output
QSPI pin data direction for the pin MISO
0 Pin direction is input
1 Pin direction is output
5
MPC561/MPC563 Reference Manual, Rev. 1.2
6
Table 15-11. DDRQS Bit Descriptions
(PQSPAR).”
7
—
8
QDDP
CS3
0000_0000_0000_0000
9
QDDP
0x30 5016
CS2
10
QDDP
Description
CS1
11
Section 15.5.2, “PORTQS Pin Assignment
QDDP
CS0
12
QDDSCK QDDMOSI QDDMISO
13
Freescale Semiconductor
14
LSB
15
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