MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 892
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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CDR3 Flash (UC3F) EEPROM
In censored mode, a UC3F EEPROM may disallow accesses to the array. If censored mode is entered by
any means then the UC3F EEPROM will exercise censorship according to
While the device remains in the uncensored mode, ACCESS may be set to allow the device to enter
censored mode and still access the UC3F array. ACCESS may not be set while the device is in censored
mode but may be cleared.
21-30
.
•
•
•
operating in peripheral mode or upon any access by an external master
operating in debug mode (BDM or Nexus)
booting from internal SRAM
ACCESS
0
0
0
0
1
FIC
X
0
0
0
1
MPC561/MPC563 Reference Manual, Rev. 1.2
CENSOR[0:1]
Table 21-9. Censorship States
01 or 10
XX
XX
11
00
Information censorship, No UC3F array accesses allowed.
No censorship, UC3F array accesses allowed.
Cleared censorship, No UC3F array accesses allowed.
Emulated censorship, No UC3F array accesses allowed.
No censorship, UC3F array accesses allowed.
Description
Table
21-9.
Freescale Semiconductor
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