MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 741
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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17.3.1
The MIOS14 requires 34 signals: 10 MDASM signals, 8 dedicated MPWMSM signals, 12 dedicated
MPIOSM signals and 4 signals are shared between the MPWMSM and MPIOSM. The required signal
function on shared signals is chosen using the PDMCR2 register in the USIU. The usage of all MIOS14
signals is shown in the block diagram of
17.3.2
The internal bus system within the MIOS14 is called the modular I/O bus (MIOB). The MIOB makes
communications possible between any submodule and the IMB3 bus master through the MBISM.
The MIOB is divided into three dedicated buses:
Freescale Semiconductor
MIRSM0
MIRSM1
Reserve
Reserve
MCPSM
Reserve
Reserve
Module
MBISM
Type
Sub-
d
d
d
d
Bloc
259-
384-
392-
400-
No.
255
256
257
258
383
391
399
511
33-
MIOS14 Signals
MIOS14 Bus System
k
BSL0=
BSL1=
CBA
0
0
Table 17-1. MIOS14 Configuration Description (continued)
BSL0=
BSL1=
Connected to:
CBB
1
0
BSL0=0
BSL1=1
CBC
MPC561/MPC563 Reference Manual, Rev. 1.2
BSL0=
BSL1=
CBD
1
1
Figure 17-1
MIRS
No.
M
Position
MIRSM
and in the configuration description of
Bit
Address
Offset
Base
6C00
6C40
0x30
6800
0x30
6810
0x30
0x30
Function
Signal
GPIO
GPIO
GPIO
GPIO
Modular Input/Output Subsystem (MIOS14)
MPIO32
MPIO32
MPIO32
MPIO32
Signal
Name
Input
B12
B13
B14
B15
MPIO32
MPIO32
MPIO32
MPIO32
Output
Signal
Name
B12
B13
B14
B15
Table
C_CNTX0
PPM_TCL
PPM_RX0
PPM_TX0
Alternate
Signal
Name
K
17-1.
17-9
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