MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 191
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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When a machine-check exception occurs, the processor does one of the following:
Which action is taken depends on the value of the MSR[ME] bit, whether or not debug mode was enabled
at reset, and (if debug mode is enabled) the values of the CHSTPE (checkstop enable) and MCIE (machine
check enable) bits in the debug enable register (DER).
processor is in the checkstop state, instruction processing is suspended and cannot be restarted without
resetting the core.
An indication is sent to the USIU which may generate an automatic reset in this condition. Refer to
Chapter 7,
The register settings for machine check exceptions are shown in
Freescale Semiconductor
•
•
•
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
Takes a machine check exception;
Enters the checkstop state; or
Enters debug mode.
MSR[ME]
“Reset,” for more details.
Register Name
0
1
0
0
1
1
Debug Mode
Table 3-25. Register Settings following a Machine Check Exception
Enable
Table 3-24. Machine Check Exception Processor Actions
0
0
1
1
1
1
1
MPC561/MPC563 Reference Manual, Rev. 1.2
CHSTPE
16:31
10:15
X
X
X
X
0
1
5:9
Bits
2:4
All
0
1
2
2
2
Set to the effective address of the instruction that caused the
interrupt
MSR0
Set to 1 for instruction fetch-related errors and 0 for
load/store-related errors
Cleared to 0
MSR[5:9]
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
MCIE
X
X
X
X
0
1
Table 3-24
Action Performed when Exception Detected
Branch to machine-check exception handler
Branch to machine-check exception handler
Table
summarizes the possibilities. When the
Enter checkstop state
Enter checkstop state
Description
Enter debug mode
Enter debug mode
3-25.
Central Processing Unit
3-47
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