MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 584
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
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Manufacturer:
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Quantity:
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QADC64E Enhanced Mode Operation
Another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue
condition occur in the same CCW. Both the pause and end-of-queue conditions are recognized
simultaneously. The end-of-queue condition has precedence so a conversion is not performed for the CCW
and the pause flag is not set. The QADC64E sets the completion flag and the queue status becomes idle.
Examples of this situation are:
14.4.4
The QADC64E queuing mechanism allows the application to utilize different requirements for
automatically scanning input channels.
In single-scan mode, a single pass through a sequence of conversions defined by a queue is performed. In
continuous-scan mode, multiple passes through a sequence of conversions defined by a queue are
executed. The possible modes are:
14.4.4.1
When the disabled mode is selected, the queue is not active. Trigger events cannot initiate queue execution.
When both queue 1 and queue 2 are disabled, wait states are not encountered for IMB3 accesses of the
RAM. When both queues are disabled, it is safe to change the QCLK prescaler values.
14.4.4.2
Reserved mode allows for future mode definitions. When the reserved mode is selected, the queue is not
active. It functions the same as disabled mode.
14-42
•
•
•
•
•
The pause bit is set in CCW10 and EOQ is programmed into CCW10
During queue 1 operation, the pause bit set in CCW32, which is also BQ2
Disabled and reserved mode
Single-scan modes
— Software initiated single-scan mode
— External trigger single-scan mode
— External gated single-scan mode
— Periodic/Interval timer single-scan mode
Continuous-scan modes
— Software initiated continuous-scan mode
— External trigger continuous-scan mode
— External gated continuous-scan mode
— Periodic/Interval timer continuous-scan mode
Scan Modes
Disabled Mode
Reserved Mode
Do not use a reserved mode. Unspecified operations may result.
MPC561/MPC563 Reference Manual, Rev. 1.2
WARNING
Freescale Semiconductor
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