MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 885
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
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Quantity:
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7. Write EHV = 0.
8. If more information needs to be programmed go to step 3.
9. Write SES = 0 in the UC3FCTL register.
State
S1
Normal Operation:
Normal array reads and register accesses. The
block protect information can be modified.
Writing EHV = 0 before HVS = 0 causes the current program sequence to
ABORT. The location for which the program sequence was aborted may not
have been programmed with sufficient margins. The block containing that
location must be erased and reprogrammed before that block of the UC3F
array may be used reliably.
Reset
Table 21-7. Program Interlock State Descriptions
Mode
T1
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 21-9. Program State Diagram
S2
S1
T2
WARNING
T6
T10
T5
T3
T7
State
Next
S2
S3
S4
T2
T9
T4
Write PE = 0, SES = 1.
Transition Requirement
T8
S5
CDR3 Flash (UC3F) EEPROM
21-23
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