MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 1120
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Internal Memory Map
B-10
1
1
0x30 4000
0x30 4002
0x30 4004
0x30 4006
0x30 4008
0x30 400A
0x30 400C
0x30 0000
0x30 0002
0x30 0004
0x30 0006
0x30 0008
0x30 000A
0x30 2000 —
0x30 37FF
Access to the DPTRAM array through the IMB3 bus is disabled once bit 5 (EMU) of either TPUMCR_A or TPUMCR_B
is set.
Access to the DPTRAM array through the IMB3 bus is disabled once bit 5 (EMU) of either TPUMCR_A or TPUMCR_B
is set.
Address
Address
Address
Access
Access
Access
U, S
U, S
S
T
T
T
S
S
S
1
S
S
S
S
S
1
1
Table B-9. Time Processor Unit 3 A and B (TPU3 A and B)
TPUMCR_A
CFSR0_A
DSCR_A
DSSR_A
Symbol
CIER_A
TICR_A
TCR_A
DPTMCR
RAMBAR
DPTRAM
DPTTCR
MISCNT
(Note: Bit descriptions apply to TPU3_B as well)
Symbol
Symbol
MPC561/MPC563 Reference Manual, Rev. 1.2
MISRH
MISRL
Table B-7. DPTRAM Control Registers
Table B-8. DPTRAM Memory Arrays
TPU3_A Module Configuration Register.
See
TPU3_A Test Configuration Register.
TPU3_A Development Support Control Register.
See
TPU3_A Development Support Status Register.
See
TPU3_A Interrupt Configuration Register.
See
TPU3_A Channel Interrupt Enable Register.
See <XrefBlue>Table 19-11 for bit descriptions.
TPU3_A Channel Function Selection Register 0.
See <XrefBlue>Table 19-12 for bit descriptions.
DPTRAM Module Configuration Register.
See
Test Configuration Register.
RAM Array Base Address Register.
See
Multiple Input Signature Register High.
Multiple Input Signature Register Low.
MISC Counter Register.
DPTRAM Memory Array
DPTRAM Control
Table 19-7
Table 19-8
Table 19-9
Table 19-10
Table 20-2
Table 20-3
TPU3_A
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
for bit descriptions.
Register
Register
Register
Freescale Semiconductor
16 only
Size
Size
Size
16
16
16
16
16
16
16
16
16
16
16
16
16
2
2
2
2
2
Reset
Reset
Reset
S, M
S, M
S, M
S, M
S, M
S, M
S, M
—
S
S
S
S
S
S
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