MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 291
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
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use the MPC561/MPC563 CLKOUT signal. This source of reset can be optionally asserted if the LOLRE
bit in the PLL, low-power, and reset control register (PLPRCR) is set. The enabled PLL loss of lock event
generates an internal hard reset sequence. Refer to
information on loss of PLL lock.
7.1.5
If the system clock is switched to the backup clock or switched from backup clock to another clock source
an internal hard reset sequence is generated. Refer to
7.1.6
When the MPC561/MPC563 software watchdog counts to zero, a software watchdog reset is asserted. The
enabled software watchdog event generates an internal hard reset sequence.
7.1.7
When the RCPU enters a checkstop state, and the checkstop reset is enabled (the CSR bit in the PLPRCR
is set), a checkstop reset is asserted. The enabled checkstop event generates an internal hard reset sequence.
Refer to the RCPU Reference Manual for more information.
7.1.8
When the development port receives a hard reset request from the development tool, an internal hard reset
sequence is generated. In this case the development tool must reconfigure the debug port. Refer to
Chapter 23, “Development
7.1.9
When the development port receives a soft reset request from the development tool, an internal soft reset
sequence is generated. In this case the development tool must reconfigure the debug port. Refer to
Chapter 23, “Development
7.1.10
When the JTAG logic asserts the JTAG soft reset signal, an internal soft reset sequence is generated. Refer
to
7.1.11
When locked bits in the PLPRCR register are changed, an internal hard reset sequence is generated. Refer
to
7.2
Table 7-1
Freescale Semiconductor
Chapter 25, “IEEE 1149.1-Compliant Interface
Chapter 8, “Clocks and Power
Reset Actions Summary
summarizes the action taken for each reset.
On-Chip Clock Switch
Software Watchdog Reset
Checkstop Reset
Debug Port Hard Reset
Debug Port Soft Reset
JTAG Reset
ILBC Illegal Bit Change
Support,” for more information.
Support,” for more information.
MPC561/MPC563 Reference Manual, Rev. 1.2
Control.”
(JTAG),” for more information.
Chapter 8, “Clocks and Power
Chapter 8, “Clocks and Power
Control,” for more
Control.”
Reset
7-3
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