MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 413

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Figure 10-12
note the following points:
Freescale Semiconductor
•
•
•
•
Total cycle length = 5, is determined as follows:
— Two clocks for basic cycle
— SCY = 1 determines 1 wait state, which is multiplied by two due to TRLX being set (2 + (SCY
— Extra clock is added due to TRLX effect on the strobes.
Because TRLX is set, assertion of the CS and WE strobes is delayed by one clock cycle.
CS assertion is delayed an additional one quarter clock cycle because ACS = 10.
The total cycle length = three clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— An extra clock cycle is required due to the effect of TRLX on the strobes.
Address
x 2)).
CLOCK
RD/WR
WE/BE
through
Data
Figure 10-11. Relaxed Timing — Read Access (ACS = 11, SCY = 1, TRLX = 1)
OE
CS
TS
TA
Figure 10-14
MPC561/MPC563 Reference Manual, Rev. 1.2
are examples of write accesses using relaxed timing. In
ACS = ‘00’ & TRLX = ‘1’
ACS = ‘11’ & TRLX = ‘1’
WEBS = ‘1’,Line Acts as BE
in Read.
Memory Controller
Figure
10-12,
10-15