MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 289
![IC MPU 32BIT 56MHZ PPC 388-PBGA](/photos/12/22/122270/mpc561mzp56_sml.jpg)
MPC561MZP56
Manufacturer Part Number
MPC561MZP56
Description
IC MPU 32BIT 56MHZ PPC 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Datasheet
1.MPC561MZP56.pdf
(1420 pages)
Specifications of MPC561MZP56
Core Processor
PowerPC
Core Size
32-Bit
Speed
56MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
64
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
388-BGA
Controller Family/series
POWER 5xx
No. Of I/o's
56
Ram Memory Size
31KB
Cpu Speed
56MHz
No. Of Timers
32
Embedded Interface Type
QSPI, SCI, UART
No. Of Pwm Channels
12
Rohs Compliant
No
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
22
Operating Supply Voltage
2.6 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC561MZP56
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC561MZP56R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Chapter 7
Reset
This section describes the MPC561/MPC563 reset sources, operation, control, and status.
7.1
The MPC561/MPC563 has several inputs to the reset logic which include the following:
All of these reset sources are fed into the reset controller. The control logic determines the cause of the
reset, synchronizes it, and resets the appropriate logic modules, depending on the source of the reset. The
memory controller, system protection logic, interrupt controller, and parallel I/O pins are initialized only
on hard reset. External soft reset initializes internal logic while maintaining system configuration.
The reset status register (RSR) reflects the most recent source to cause a reset.
7.1.1
The power-on reset pin, PORESET, is an active low input. In a system with power-down low-power mode,
this pin should be activated only as a result of a voltage failure on the KAPWR pin. After detecting the
assertion of PORESET, the MPC561/MPC563 enters the power-on reset state. During this state the
MODCK[1:3] signals determine the oscillator frequency, PLL multiplication factor, and the PITRTCLK
and TMBCLK clock sources. In addition, the MPC561/MPC563 asserts the SRESET and HRESET pins
at the rising edge of PORESET.
The PORESET pin should be asserted for a minimum time of 100,000 of clock oscillator cycles after a
valid level has been reached on the KAPWR supply. After detecting the assertion of PORESET, the
MPC561/MPC563 remains in the power-on reset state until the last of the following two events occurs:
Freescale Semiconductor
•
•
•
•
•
•
•
•
•
•
•
Power-on reset
External hard reset pin (HRESET)
External soft reset pin (SRESET)
Loss of PLL lock
On-chip clock switch
Software watchdog reset
Checkstop reset
Debug port hard reset
Debug port soft reset
JTAG reset
Illegal bit change (ILBC)
Reset Operation
Power-On Reset
MPC561/MPC563 Reference Manual, Rev. 1.2
7-1
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