MPC561MZP56 Freescale Semiconductor, MPC561MZP56 Datasheet - Page 836

• Manufacturer Part Number: MPC561MZP56
• Description: IC MPU 32BIT 56MHZ PPC 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC561MZP56

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 56MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 388-BGA
• Controller Family/series: POWER 5xx
• No. Of I/o's: 56
• Ram Memory Size: 31KB
• Cpu Speed: 56MHz
• No. Of Timers: 32
• Embedded Interface Type: QSPI, SCI, UART
• No. Of Pwm Channels: 12
• Rohs Compliant: No
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 22
• Operating Supply Voltage: 2.6 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No

Time Processor Unit 3
Figure 19-3
19-6
— If the enhanced prescaler is selected (EPSCKE = 1), the EPSCK bits select a value by which
— The output of either the standard prescaler or the enhanced prescaler is then divided by 1, 2, 4,
— If the TPUMCR2[DIV2] bit is one, the TCR1 counter increments at a rate of the internal clock
the system clock is divided. The lowest frequency for TCR1 clock is system clock divided by
64x8. The highest frequency for TCR1 clock is system clock divided by two (2x1). See
Table 19-2
or 8, depending on the value of the TCR1P field in the TPUMCR.
divided by two. If DIV2 is zero, the TCR1 increment rate is defined by the output of the TCR1
prescaler (which, in turn, takes as input the output of either the standard or enhanced prescaler).
shows a diagram of the TCR1 prescaler control block.
and
Table
Table 19-2. Enhanced TCR1 Prescaler Divide Values
0x04, 0x05,...0x1d
EPSCK Value
MPC561/MPC563 Reference Manual, Rev. 1.2
19-3.
0x00
0x01
0x02
0x03
0x1e
0x1f
Table 19-3. TCR1 Prescaler Values
TCR1P Value
0b00
0b01
0b10
0b11
Divide by
Divide System Clock By
1
2
4
8
10,12,...60
62
64
2
4
6
8
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