ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 122

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

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Atmel ATmega16/32/64/M1/C1
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICRn or
OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and the
maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM resolution in bits can be
calculated by using the following equation:
In fast PWM mode the counter is incremented until the counter value matches either one of
the fixed values 0x00FF, 0x01FF, or 0x03FF (WGMn3:0 = 5, 6, or 7), the value in ICRn
(WGMn3:0 = 14), or the value in OCRnA (WGMn3:0 = 15). The counter is then cleared at the
following timer clock cycle. The timing diagram for the fast PWM mode is shown in
13-7. The figure shows fast PWM mode when OCRnA or ICRn is used to define TOP. The
TCNTn value is in the timing diagram shown as a histogram for illustrating the single-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal
line marks on the TCNTn slopes represent compare matches between OCRnx and TCNTn.
The OCnx Interrupt Flag will be set when a compare match occurs.
Figure 13-7. Fast PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOVn) is set each time the counter reaches TOP. In addi-
tion the OCnA or ICFn Flag is set at the same timer clock cycle as TOVn is set when either
OCRnA or ICRn is used for defining the TOP value. If one of the interrupts are enabled, the
interrupt handler routine can be used for updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNTn and the OCRnx.
Note that when using fixed TOP values the unused bits are masked to zero when any of the
OCRnx Registers are written.
The procedure for updating ICRn differs from updating OCRnA when used for defining the
TOP value. The ICRn Register is not double buffered. This means that if ICRn is changed to a
low value when the counter is running with none or a low prescaler value, there is a risk that
the new ICRn value written is lower than the current value of TCNTn. The result will then be
that the counter will miss the compare match at the TOP value. The counter will then have to
count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare
match can occur. The OCRnA Register however, is double buffered.
R
FPWM
TCNTn
OCnx
OCnx
Period
=
log
---------------------------------- -
log
TOP
1
2
+
1
2
3
4
5
6
7
8
OCRnx/TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
(COMnx1:0 = 2)
(COMnx1:0 = 3)
7647G–AVR–09/11
Figure