ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 321

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

26.7
7647G–AVR–09/11
SPI Timing Characteristics
See
Table 26-4.
Note:
Figure 26-3. SPI Interface Timing Requirements (Master Mode)
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Figure 26-3
(Data Output)
In SPI Programming mode the minimum SCK high/low period is:
- 2 t
- 3 t
(Data Input)
(CPOL = 0)
(CPOL = 1)
SS high to tri-state
CLCL
CLCL
SCK to out high
SCK high/low
SCK to SS high
SS low to SCK
MISO
MOSI
Rise/Fall time
Rise/Fall time
SCK high/low
SS low to out
Description
SCK
SCK
SCK period
SCK period
Out to SCK
SCK to out
SCK to out
SPI Timing Parameters
SS
for f
for f
Setup
Setup
and
Hold
Hold
CK
CK
Figure 26-4
< 12MHz
>12MHz
(1)
6
4
MSB
5
MSB
for details.
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Atmel ATmega16/32/64/M1/C1
7
4 • t
2 • t
Min.
10
20
20
t
ck
...
ck
ck
...
See
50% duty cycle
0.5 • t
Table 15-4
Typ.
3.6
2
10
10
10
10
15
15
10
sck
LSB
1
LSB
2
Max.
1600
3
8
ns
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