ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 273

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

21.4.2
21.4.2.1
7647G–AVR–09/11
Digital to Analog Converter input Register – DACH and DACL
DALA = 0
In accordance with the
the update of the DAC input values. The update will be generated by the rising edge of the
selected interrupt flag whether the interrupt is enabled or not.
Table 21-1.
• Bit 2 – DALA: Digital to Analog Left Adjust
Set this bit to left adjust the DAC input data.
Clear it to right adjust the DAC input data.
The DALA bit affects the configuration of the DAC data registers. Changing this bit affects the
DAC output on the next DACH writing.
• Bit 1 – DAOE: Digital to Analog Output Enable bit
Set this bit to output the conversion result on D2A,
Clear it to use the DAC internally.
• Bit 0 – DAEN: Digital to Analog Enable bit
Set this bit to enable the DAC,
Clear it to disable the DAC.
When the DAC is used with a 10-bit output value, the value is written into the 16-bit register
pair DACH:DACL as two separate 8-bit writes. As such the DAC value should be written first
the low byte to DACL followed by the high byte value to DACH. Only when the DACH register
is written is the DAC value updated.
If you choose to use the DAC in left-adjust 8-bit mode then a single write to the DACH register
with the 8-bit value will suffice to update the DAC.
Bit
Read/Write
Initial Value
DATS2
0
0
0
0
1
1
1
1
DAC Auto Trigger source selection
DATS1
0
0
1
1
0
0
1
1
DAC7
R/W
R/W
7
0
0
-
Table
DAC6
R/W
R/W
6
0
0
-
DATS0
0
1
0
1
0
1
0
1
18-7, these 3 bits select the interrupt event which will generate
DAC5
R/W
R/W
5
0
0
-
Atmel ATmega16/32/64/M1/C1
DAC4
Description
Analog comparator 0
Analog comparator 1
External Interrupt Request 0
Timer/Counter0 Compare Match
Timer/Counter0 Overflow
Timer/Counter1 Compare Match B
Timer/Counter1 Overflow
Timer/Counter1 Capture Event
R/W
R/W
4
0
0
-
DAC3
R/W
R/W
3
0
0
-
DAC2
R/W
R/W
2
0
0
-
DAC9
DAC1
R/W
R/W
1
0
0
DAC8
DAC0
R/W
R/W
0
0
0
DACH
DACL
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