ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 284

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

24.5.1
284
Atmel ATmega16/32/64/M1/C1
Store Program Memory Control and Status Register – SPMCSR
The Store Program Memory Control and Status Register contains the control bits needed to
control the Boot Loader operations.
• Bit 7 – SPMIE: SPM Interrupt Enable
When the SPMIE bit is written to one, and the I-bit in the Status Register is set (one), the SPM
ready interrupt will be enabled. The SPM ready Interrupt will be executed as long as the
SPMEN bit in the SPMCSR Register is cleared.
• Bit 6 – RWWSB: Read-While-Write Section Busy
When a Self-Programming (Page Erase or Page Write) operation to the RWW section is initi-
ated, the RWWSB will be set (one) by hardware. When the RWWSB bit is set, the RWW
section cannot be accessed. The RWWSB bit will be cleared if the RWWSRE bit is written to
one after a Self-Programming operation is completed. Alternatively the RWWSB bit will auto-
matically be cleared if a page load operation is initiated.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three
clock cycles will read a byte from the signature row into the destination register. see
the Signature Row from Software” on page 289
cycles after SIGRD and SPMEN are set will have no effect. This operation is reserved for
future use and should not be used.
• Bit 4 – RWWSRE: Read-While-Write Section Read Enable
When programming (Page Erase or Page Write) to the RWW section, the RWW section is
blocked for reading (the RWWSB will be set by hardware). To re-enable the RWW section, the
user software must wait until the programming is completed (SPMEN will be cleared). Then, if
the RWWSRE bit is written to one at the same time as SPMEN, the next SPM instruction
within four clock cycles re-enables the RWW section. The RWW section cannot be re-enabled
while the Flash is busy with a Page Erase or a Page Write (SPMEN is set). If the RWWSRE bit
is written while the Flash is being loaded, the Flash load operation will abort and the data
loaded will be lost.
• Bit 3 – BLBSET: Boot Lock Bit Set
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four
clock cycles sets Boot Lock bits and Memory Lock bits, according to the data in R0. The data
in R1 and the address in the Z-pointer are ignored. The BLBSET bit will automatically be
cleared upon completion of the Lock bit set, or if no SPM instruction is executed within four
clock cycles.
An LPM instruction within three cycles after BLBSET and SPMEN are set in the SPMCSR
Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into
the destination register. See
details.
Bit
Read/Write
Initial Value
SPMIE
R/W
7
0
RWWSB
R
6
0
“Reading the Fuse and Lock Bits from Software” on page 288
SIGRD
R
5
0
RWWSRE
R/W
4
0
BLBSET
R/W
for details. An SPM instruction within four
3
0
PGWRT
R/W
2
0
PGERS
R/W
1
0
SPMEN
R/W
0
0
7647G–AVR–09/11
“Reading
SPMCSR
for