ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 133

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

13.10.3
13.10.4
13.10.5
7647G–AVR–09/11
Timer/Counter1 Control Register C – TCCR1C
Timer/Counter1 – TCNT1H and TCNT1L
Output Compare Register 1 A – OCR1AH and OCR1AL
If external pin modes are used for the Timer/Countern, transitions on the Tn pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
• Bit 7 – FOCnA: Force Output Compare for Channel A
• Bit 6 – FOCnB: Force Output Compare for Channel B
The FOCnA/FOCnB bits are only active when the WGMn3:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCRnA is written when operating in a PWM mode. When writing a logical one to the
FOCnA/FOCnB bit, an immediate compare match is forced on the Waveform Generation unit.
The OCnA/OCnB output is changed according to its COMnx1:0 bits setting. Note that the
FOCnA/FOCnB bits are implemented as strobes. Therefore it is the value present in the
COMnx1:0 bits that determine the effect of the forced compare.
A FOCnA/FOCnB strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCRnA as TOP.
The FOCnA/FOCnB bits are always read as zero.
The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Regis-
ter (TEMP). This temporary register is shared by all the other 16-bit registers.
16-bit Registers” on page 109.
Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a
compare match between TCNTn and one of the OCRnx Registers.
Writing to the TCNTn Register blocks (removes) the compare match on the following timer
clock for all compare units.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
FOC1A
R/W
R/W
R/W
7
0
7
0
7
0
FOC1B
R/W
R/W
R/W
6
0
6
0
6
0
R/W
R/W
R
5
–
0
5
0
5
0
Atmel ATmega16/32/64/M1/C1
R/W
R/W
R
4
–
0
4
OCR1A[15:8]
0
4
0
TCNT1[15:8]
OCR1A[7:0]
TCNT1[7:0]
R/W
R/W
R
3
–
0
3
0
3
0
R/W
R/W
R
2
0
2
–
0
2
0
R/W
R/W
R
1
–
0
1
0
1
0
R/W
R/W
See “Accessing
R
0
–
0
0
0
0
0
TCCR1C
OCR1AH
OCR1AL
TCNT1H
TCNT1L
133