ATMEGA64M1-15MZ Atmel, ATMEGA64M1-15MZ Datasheet - Page 352

• Manufacturer Part Number: ATMEGA64M1-15MZ
• Description: MCU AVR 64KB FLASH 3PSC 32-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA64M1-15MZ

• Package / Case: 32-VQFN
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 11x10b; D/A 1x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Connectivity: CAN, LIN, SPI, UART/USART
• Core Size: 8-Bit
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATADAPCAN01
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Lead Free Status / Rohs Status: Details

30.1.4
352
Atmel ATmega16/32/64/M1/C1
Errata Description
1. Inopportune reset of the CANIDM registers
2. The AMPCMPx bits return 0
3. No comparison when amplifier is used as comparator input and ADC input
4. CRC calculation of diagnostic frames in LIN 2.x.
After the reception of a CAN frame in a MOb, the ID mask registers are reset.
Problem fix / workaround
Before enabling a MOb in reception, re-initialize the ID mask registers -
CANIDM[4..1].
When they are read the AMPCMPx bits in AMPxCSR registers return 0.
Problem fix / workaround
If the reading of the AMPCMPx bits is required, store the AMPCMPx value in a vari-
able in memory before writing in the AMPxCSR register and read the variable when
necessary.
When it is selected as ADC input, an amplifier receives no clock signal when the ADC
is stopped. In that case, if the amplifier is also used as comparator input, no analog
signal is propagated and no comparison is done.
Problem fix / workaround
Select another ADC channel rather than the working amplified channel.
Diagnostic frames of LIN 2.x use “classic checksum” calculation. Unfortunately, the
setting of the checksum model is enabled when the HEADER is transmitted/received.
Usually, in LIN 2.x the LIN/UART controller is initialized to process “enhanced check-
sums” and a slave task does not know what kind of frame it will work on before
checking the ID.
Problem fix / workaround
This workaround is to be implemented only in case of transmission/reception of diag-
nostics frames.
a. Slave task of master node:
b. For slaves nodes, the workaround is in 2 parts:
The time-out counter is disabled during the RESPONSE when the workaround is set.
– Once the RESPONSE is received or sent (having RxOK or TxOK as well as
Before enabling the HEADER, the master must set the appropriate LIN13 bit-
value in LINCR register.
– Before enabling the RESPONSE, use the following function:
unsigned char
}
void
}
void
LERR), use the following function:
temp = LINBTR;
LINCR = 0x00;
LINBTR = (1<<LDISR)|temp;
LINCR
LINDLR = 0x88;
LINCR = 0x00;
LINBTR = 0x00;
LINCR
lin_wa_tail(void)
lin_wa_head(void) {
= (1<<LIN13)|(1<<LENA)|(0<<LCMD2)|(0<<LCMD1)|(0<<LCMD0);
= (0<<LIN13)|(1<<LENA)|(0<<LCMD2)|(0<<LCMD1)|(0<<LCMD0);
temp;
// It is not a RESET !
// If it isn't already done
// It is not a RESET !
{
7647G–AVR–09/11